The present invention relates to a semiconductor device and particularly to a semiconductor integrated circuit device having excellent low voltage operation characteristics.
In this specification, reference is made to the following cited references identified with the reference numbers.
[Reference 1] xe2x80x9cVLSI Memory Designxe2x80x9dKiyoo Itoh, p162;
[Reference 2] xe2x80x9cJapanese Patent Laid-open No. Hei 2-24898 (corresponding U.S. Pat. No. 4,973,864);
[Reference 3] xe2x80x9cJapanese Patent Laid-open No. Hei 10-3971 (corresponding U.S. Pat. No. 5,854,562);
[Reference 4] xe2x80x9c1996 Symposium on VLSI Circuits Digests of Technical Papers, pp. 104-105;
FIG. 26.1 of the [Reference 1] is a sensing system circuit diagram of the standard DRAM (Dynamic Random Access Memory). This diagram is a so-called shared sense-amplifier structure (having the structure where one sense amplifier line is used in common by the right and left memory mats). FIG. 18 shows a circuit diagram where this structure is omitted. A C100 and a M100 form a memory cell wherein the M100 indicates a charge transfer NMOS transistor, while VPL indicates a plate voltage. BL[n], /BL[n] are bit lines, WL[m] is word line, and a memory cell is disposed at an adequate intersection to form a memory array MA100. M101, M102, M103 are NMOS transistors and VBM is a power source voltage equal to a half of the data line voltage VDL. These elements are precharge circuit 101 of the so-called half VDD precharge system for precharging the bit line to the VBM potential by turning ON the M103 from the M101. M200, M201 are PMOS transistors, while M202, M203 are NMOS transistors, forming a CMOS latch type sense amplifier 201. Moreover, M109 and M110 are NMOS transistors to form a Y switch 103a to selectively connect the bit lines BL[n], /BL[n] to the global bit lines GBL[p], /GBL[p] by turning ON the M109 and M110.
FIG. 19 shows waveforms for the read operation of this memory. Here, an array voltage VDL is set to a voltage which is equal to the power source voltage VDD assumed as 1.0V. Moreover, the power source voltage VBM is assumed as 0.5V which is equal to a half of such power source voltage and a setup voltage of the word line is assumed as 2.5V.
A precharge signal EQ is negated at the time T0 and a word line WL[m] is asserted at the time T1. Thereby, the MOS transistor M100 in the memory cell selected by such word line turns ON to share the charges accumulated in the capacitor C100 within the memory cell and a parasitic capacitance added to the bit lines BL[n], /BL[n] in order to generate a potential difference Vs for reflecting information within the memory cell on the bit lines BL[n], /BL[n].
Since the sense amplifier activate signals CSP and CSN are respectively driven to 1.0V and 0V, the bit line potentials BL[n], /BL[n] are amplified up to 1.0V and 0V. In this figure, since a YS[k] is asserted, a Y switch is turned ON and the global bit lines GBL[p], /GBL[p] are also amplified simultaneously when the bit lines BL[n], /BL[n] are amplified.
The signal /BL[n] which is given the slash sign xe2x80x9c/xe2x80x9d before BL[n] among the signals explained above depends on the generally used expression method and this signal /BL[n] means a complementary signal of BL[n]. Moreover, a bracket [ ] is also the generally used expression method and the signal BL[n], for example, means the typical expression of signals of bus structure consisting of one or more signal lines such as BL[0], BL[1], BL[2]. This expression method is used in this specification.
FIG. 20(A) shows a result of simulation of sensing rate (tSENSE) of the sensing system circuit of DRAM of FIG. 8 conducted by the inventors of the present invention. The sensing rate (tSENSE) is defined, as shown in FIG. 20(B), as the time required until a potential difference of the bit lines BL, /BL is amplified up to the 60% of the power source voltage VDD from activation of the sensing amplifier. Temperature is assumed as two kinds of temperatures of xe2x88x9240xc2x0 C. and 125xc2x0 C. in terms of the junction temperature Tj. This analysis by the inventors of the present invention has proved as follows.
(A1) The sense time (tSENSE) is remarkably delayed as the power source voltage is lowered.
(A2) When the power source voltage is equal to about 1.2V or less, the sense time in the higher temperature is further than that in the lower temperature. It is because a drive current of the sensing amplifier is mainly governed with a diffusion current, in place of a drift current, among the drain current of the MOS transistor. In general, the diffusion current very sensitively changes for temperature and a threshold value of MOS transistor. Therefore, when a sense amplifier is used in the area where the diffusion current governs the operation in place of the drift current, a sensing time changes to a large extent for fluctuation of manufacturing process of LSI and fluctuation of operation environment. This event may grow up to a problem that an yield rate of an LSI circuit is lowered. As a result, cost of LSI using DRAM of the circuit of such structure rises.
Moreover, FIG. 20(C) shows dependence of a delay time of a CMOS inverter on a power source voltage as an example of a delay time characteristic (tDLAY) of an ordinary CMOS logic circuit. Temperature is assumed as two kinds of temperatures of xe2x88x9240xc2x0 C. and 125xc2x0 C. in terms of junction temperature Tj as in the case of FIG. 20(A). This analysis by the inventors of the present invention has proved as follows.
(B1) Deterioration in the operation rate when the power source voltage is lowered is remarkably smaller than that of the sensing system of the existing DRAM shown in FIG. 18.
(B2) The temperature characteristic in the lower voltage condition is different in the CMOS inverter and the sensing system of the existing DRAM shown in FIG. 18.
From this fact, it can be understood that the DRAM circuit including the existing sensing system shown in FIG. 18 and the logic circuit having the delay characteristic shown in FIG. 20(C) are not matched with each other through the low voltage characteristics thereof. Here, matching of a plurality of circuits means that dependence of delay characteristic on the power source voltage and temperature is similar. For example, when the power source voltage is set to a lower value, the operation rate of all circuits is delayed in the similar degree and when the temperature is lowered, the operation rate of all circuits is also delayed in the similar degree.
When the DRAM including the existing sensing system as shown in FIG. 18 and a logic circuit which are not matched are disposed simultaneously on the same LSI, the operation rate during a low voltage operation of the logic LSI including such DRAM is governed with the characteristic that operation rate of the DRAM is rather low under the lower temperature. For example, the operation rate of the LSI as a whole is governed with the racing. Moreover, when the logic LSI including such DRAM is used in a plurality of operation modes where the power source voltage and the operating frequency vary, the operating frequency in the low voltage operation mode is extremely delayed because the DRAM is included.
Therefore, it is an object of the present invention to provide a sense amplifier which stably operates even under the low voltage condition.
A typical structure of the present invention is as follows. Namely, a semiconductor device comprises a word line (WL), a first bit line pair (BL, /BL), a memory cell (MC) provided at an intersection of the word line and the first bit line pair, a second bit line pair (LBL, /LBL), switch circuits (ISO_SW_T, ISO_SW_B) for coupling the first bit line pair and second bit line pair, a sense amplifier including a first circuit (PSA) connected to the first bit line pair and a second circuit (MSA) connected to the second bit line pair, a first precharge circuit (PC1) for precharging the first bit line pair to a first precharge potential and a second precharge circuit (PC2) for precharging the second bit line pair to a second precharge potential, wherein the second circuit is a circuit for amplifying one of the first bit line pair and one of second bit line pair to a first potential (VSS) receiving a storage signal of the memory cell and the other pair to a second potential (VDL), the first precharge potential is a voltage (VBM) between the first potential and the second potential and the second precharge potential is equal to the second potential.
Moreover, according to the other aspect of the present invention, a semiconductor device comprises a word line (WL) a first bit line pair (BL, /BL), a memory cell (MC) provided at an intersection of the word line and first bit line pair, a capacitor pair including a first capacitor (C250) having a first electrode connected to one of the first bit line pair and a second electrode connected to one of the second bit line pair and a second capacitor (C251) having a third electrode connected to the other of the first bit line pair and a fourth electrode connected to the other of the second bit line pair, a switch circuit including a first switch (M206) for connecting one of the first bit line pair and one of the second bit line pair and a second switch (M207) for connecting the other of the first bit line pair and the other of the second bit line pair, a sense amplifier (SA) connected to the second bit line pair, a first precharge circuit (PC1) for precharging the first bit line pair to a first precharge potential and a second precharge circuit (PC2) for precharging the second bit line pair to a second precharge potential.